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NCP5203 2-in-1 DDR Power Controller
The NCP5203 2-in-1 DDR Power Controller is a complete power solution for an ACPI compliant high current DDR memory system. This IC combines the efficiency of a PWM controller for the VDDQ supply with the simplicity of linear regulator for the VTT termination voltage. The NCP5203 contains a synchronous PWM buck controller for driving two external NFETs to form the DDR memory supply voltage (VDDQ). The $2.0 A user adjustable VTT terminator regulator has short circuit protection. An internal power good function monitors both the VDDQ and VTT outputs and signals if a fault occurs. Protective features include soft-start, undervoltage monitoring of 5VDUAL, over protection current (OCP), and thermal shutdown. The IC is packaged in 18-lead QFN.
Features http://onsemi.com MARKING DIAGRAM
18 1 18-LEAD QFN, 5 x 6 mm MN SUFFIX CASE 505 1
NCP5203 AWLYYWW
* * * * * * * * * * * * * * *
Supports DDR I and DDR II Incorporates VDDQ, VTT Regulators Operates from Single 5 V Supply VTT Regulator includes Integrated Power FETs Sourcing/Sinking up to 2.0 A All External Power MOSFETs are N-Channel Adjustable VDDQ Adjustable VTT Fixed Switching Frequency of 300 kHz for VDDQ in S0 Fixed Switching Frequency of 600 kHz for VDDQ in S3 Soft-Start Protection for VDDQ Undervoltage Monitor of 5VDUAL Short-Circuit Protection for VDDQ and VTT Thermal Shutdown Housed in QFN-18 Pb-Free Package is Available*
A WL YY WW
= Assembly Location = Wafer Lot = Year = Work Week
PIN CONNECTIONS
VDDQEN VTTEN PGOOD REFSNS FBVTT AGND SS COMP FBDDQ
1 2 3 4 5 6 7 8 9
18 17 16 15 14 13 12 11 10
VDDQ VTT PGND BST BGDDQ TGDDQ 5VDUAL SWDDQ OCDDQ
Typical Applications
* DDR Memory Supply and Termination Voltage * Active Termination Busses (SSTL-2, SSTL-3)
ORDERING INFORMATION
Device NCP5203MNR2 NCP5203MNR2G Package QFN QFN (Pb-Free) Shipping 2500 Tape & Reel 2500 Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2005
1
January, 2005 - Rev. 1
Publication Order Number: NCP5203/D
NCP5203
CL1 VTTEN VDDQEN VTTEN RL1 VDDQEN OCDDQ BST
5VDUAL
5VDUAL
5VDUAL
PGOOD PGOOD SS CSS NCP5203 SWDDQ VTT 1.25 V, 2.0 A Peak COUT2 VTT FBVTT BGDDQ PGND M2 COUT1 TGDDQ M1 L VDDQ 2.5V, 15A
COMP
CZ1 RZ1
CP1
CZ2 RZ2 R1
R3 REFSNS AGND R4
FBDDQ R2 VDDQ
Figure 1. Typical Application Diagram
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5VDUAL VREF VREFGD TSD CBULK VBST BST RL1 + - TGDDQ PGND FBDDQ R14 VREF R15 VBST BGDDQ VREF UVLO + FBDDQ PWM- COMP - + VREF AMP A - 5VDUAL SC2PWR + - VTT Regulation Control PGND 5VDUAL COUT2 M2 PGND PGND PGND FBVTT M1 + - R17 R16 PGND OSC M4 COUT1 L OVLO + - VDDQ SWDDQ VBST M3 CBST IREF OCDDQ CDCPL Thermal Shutdown LIN
5VDUAL
5VDUAL
VDDQEN 5VDL GD FAULT 5VDUAL UVLO + INREGVTT - INREGDDQ ILIM Control Logic
Voltage and Current Reference
VTTEN
5VDUAL
5VDUAL
VDDQS0 VDDQS3 VTTS0 VTTS3
R10
VREF
R11
5VDUAL
SS VDDQ PWM Logic VDDQS0 VDDQS3
CSS
5VDUAL
R5
NCP5203
Figure 2. Detailed Block Diagram
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SC2GND + - VTTS0 VTTS3 INREGDDQ INREGVTT
3
PGOOD
PGND
COMP CZ1 RZ1 FBDDQ REFSNS VDDQ VTT VTT R4 R3 R1 CP1 CZ2 RZ2 R2
GND
AGND
NCP5203
PIN FUNCTION DESCRIPTION
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Symbol VDDQEN VTTEN PGOOD REFSNS FBVTT AGND SS COMP FBDDQ OCDDQ SWDDQ 5VDUAL TGDDQ BGDDQ BST PGND VTT VDDQ VDDQ regulator enable input. Active high. VTT regulator enable input. Active high. Power good signal open-drain output. Reference voltage input of VTT regulator. VTT regulator feedback pin for closed loop regulation. Analog ground connection and remote ground sense. Soft-start capacitor connection to ground. VDDQ error amplifier compensation node. VDDQ regulator feedback pin for closed loop regulation. Overcurrent sense and program input for the high-side FET of VDDQ regulator. VDDQ regulator inductor driven node and current limit sense input. 5VDUAL supply input. Gate driver output for DDQ regulator high-side N-Channel power FET. Gate driver output for DDQ regulator low-side N-Channel power FET. Supply input of VDDQ regulator and 5 V boost capacitor connection. Power ground. VTT regulator output. Power input for VTT regulator. Description
MAXIMUM RATINGS (Note 1)
Rating Power Supply Voltage (Pin 12, 18) Gate Drive Supply/Output Voltage (Pin 13, 14, 15) Switch DDQ (Pin 11) Input/Output Pins (Pin 1, 2, 7; 4, 5, 17; 3, 8, 9, 10) Thermal Characteristics QFN-18 Plastic Package Thermal Resistance Junction-to-Ambient Operating Junction Temperature Range Operating Ambient Temperature Range Storage Temperature Range Moisture Sensitivity Level Electro Static Discharge (ESD) Human Body Model Machine Model Symbol 5VDUAL VBST, Vg SWDDQ VIO Value -0.3, 6.5 -0.3, 14 -1.0, 5VDUAL -0.3, 6.5 Unit V V V V C/W RqJA TJ TA Tstg MSL HBM MM 35 0 to +150 0 to +70 -55 to +150 2.0 2.0 200 C C C - kV V
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. All voltages are with respect to AGND (Pin 6) and PGND (Pin 16).
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NCP5203
ELECTRICAL CHARACTERISTICS (5VDUAL = 5.0 V, TA = 0 to 70C)
Characteristic Supply Voltage 5VDUAL Operating Voltage BST Operating Voltage Supply Current Quiescent Supply Current (5VDUAL) Shutdown Current Undervoltage Monitor 5VDUAL UVLO Lower Threshold 5VDUAL UVLO Hysteresis Thermal Shutdown Thermal Trip Point VDDQ Switching Regulator FBDDQ Feedback Voltage, Control Loop in Regulation Feedback Input Current Oscillator Frequency in S0 Mode Oscillator Frequency in S3 Mode Ramp-Amplitude Voltage OCDDQ Pin Current Sink OCDDQ Pin Current Sink Temperature Coefficient Minimum Duty Cycle Maximum Duty Cycle Soft-start Current Overvoltage Trip Threshold Undervoltage Trip Threshold Error Amplifier DC Gain Unity Gain Bandwidth Slew Rate Gate Drivers TGDDQ Gate Pull-HIGH Resistance TGDDQ Gate Pull-LOW Resistance BGDDQ Gate Pull-HIGH Resistance BGDDQ Gate Pull-LOW Resistance 2. Guaranteed by design, not tested in production. IOUT = 400 mA, VBST = 10 V IOUT = 400 mA, VBST = 10 V IOUT = 400 mA, VBST = 10 V IOUT = 400 mA, VBST = 10 V - - - - 3.5 2.5 3.5 1.3 - - - - W W W W (Note 2) COMP_GND = 220 nF, 1.0 W in series (Note 2) COMP_GND = 10 pF (Note 2) - - - 70 2.0 8.0 - - - dB MHz V/mS TA = 0 to 70_C TA = 25_C VFBDDQ = 1.25 V VDDQEN = VTTEN = 5 V VDDQEN = 5 V, VTTEN = 0 V At Max Duty Cycle VOCDDQ = 4.0 V, TA = 25_C (Note 2) - - DDQEN = 5.0 V; VSS = 0 V With respect to Error Comparator Threshold With respect to Error Comparator Threshold 1.225 1.232 - 262.5 500 - 23 - 0 - 3.5 115 - 1.25 1.25 - 300 600 1.25 35 3200 - 90 5.0 130 65 1.275 1.268 1.0 337.5 700 - 47 - - - 6.5 - 75 V mA kHz kHz V mA ppm/_C % % mA % % (Note 2) - 150 - _C Falling Edge - 3.6 - 3.95 0.2 4.3 - V V - VDDQEN = 0 V, VTTEN = 0 V - - 5.0 - 10 1.0 mA mA - - 4.5 4.0 5.0 10 5.5 13.2 V V Test Conditions Min Typ Max Unit
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NCP5203
ELECTRICAL CHARACTERISTICS (continued) (5VDUAL = 5.0 V, TA = 0 to 70C)
Characteristic VTT Active Terminator VTT with Respect to REFSNS REFSNS - VTT, IOUT = 0 to 2.0 A (Sink Current) IOUT = 0 to -2.0 A (Source Current) - - mV -30 - - 2.05 - - -2.5 2.75 - 30 -2.05 - A A Test Conditions Min Typ Max Unit
Source Current Limit Sink Current Limit Control Section VDDQEN Pin Threshold High VDDQEN Pin Threshold Low VDDQEN Pin Input Current VTTEN Pin Threshold High VTTEN Pin Threshold Low VTTEN Pin Input Current PGOOD Pin ON Resistance PGOOD Pin OFF Current
- - VDDQEN = 5 V - - VDDQEN = VTTEN = 5 V I_PGOOD = 5.0 mA -
1.4 - - 1.4 - - - -
- - 5.0 - - 5.0 80 -
- 0.5 - - 0.5 - - 1.0
V V mA V V mA W mA
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NCP5203
DETAILED OPERATING DESCRIPTION
General
The NCP5203 2-in-1 DDR Power Controller combines the efficiency of a VDDQ PWM controller with the simplicity of a linear regulator for VTT termination. Both VDDQ and VTT outputs can be user adjusted. The inclusion of both VDDQ and VTT power good voltage monitors, soft-start, VDDQ overvoltage and undervoltage detection, supply undervoltage monitors, and thermal shutdown, makes this device a total power solution for high current DDR memory systems.
VDDQ Switching Regulator in Normal (S0) Mode
The VDDQ regulator is a switching synchronous rectification buck controller directly driving two external N-Channel power FETs. An external resistor divider sets the nominal output voltage. The control architecture is voltage mode fixed frequency PWM (300 kHz 12.5%) with external compensation. The VDDQ output voltage is divided down and fed back to the inverting input of an internal amplifier through the FBDDQ pin to close the loop at VDDQ = VFBDDQ x (1 + R2/R1). This amplifier compares the feedback voltage with an internal VREF1 (= 1.25 V) to generate an error signal for the PWM comparator. This error signal is further compared with a
Table 1. State, Operation, Input and Output Condition Table
USER INPUTS MODE S5 S0 S3 S5 5VDUAL UVLO Low High High High VDDQEN X High High Low VTTEN X High Low X
fixed frequency Ramp waveform derived from the internal oscillator to generate a pulse-width-modulated signal. This PWM signal drives the external N-Channel Power FETs via the TGDDQ and BGDDQ pins. External inductor L and capacitor COUT1 filter the output. The VDDQ output voltage ramps up at a pre-defined soft-start rate each time the IC exits S5. When in normal mode, and regulation of VDDQ is detected, signal INREGDDQ will go high to notify the control logic block. For enhanced efficiency, an active synchronous switch is used to eliminate the conduction loss contributed by the forward voltage of a diode or Schottky diode rectifier. Adaptive non-overlap timing control of the complementary gate drive output signals is provided to reduce shoot-through current.
Tolerance of VDDQ
The tolerance of VFBDDQ and the ratio of the external resistor divider R2/R1 both impact the precision of VDDQ. When the control loop is in regulation, VDDQ = VFBDDQ x (1 + R2/R1). With a worst case (overtemperature) VFBDDQ tolerance of 2%, a worst case range of 2.5% for VDDQ will be assured if the ratio R2/R1 is specified as 0.98985 1%.
OPERATING CONDITIONS VDDQ H-Z Normal Standby H-Z VTT H-Z Normal H-Z H-Z
OUTPUT CONDITIONS TGDDQ Low Normal (300 kHz) Normal (600 kHz) Low BGDDQ Low Normal (300 kHz) Low Low PGOOD Low H-Z Low Low
VDDQ Regulator in Standby Mode (S3)
During S3, the VDDQ regulator operates in asynchronous switch mode. The switching frequency is increased to 600 kHz, the low-side FET is disabled, and the body diode of the low side FET is used. The regulator will operate in discontinuous conduction mode (DCM) and the switching frequency is doubled to reduce peak conduction current.
VDDQ Regulator Fault Protection
across this resistor. This voltage is compared to the voltage at SWDDQ pin when the TGDDQ is high after a fixed blanking period of 500 ns to avoid false current limit triggering. When the voltage at SWDDQ is lower than OCDDQ, an overcurrent condition occurs, upon which all outputs will be latched off to protect against a short-to-ground condition on SWDDQ or VDDQ. The IC will be reset once 5VDUAL or VDDQEN is cycled.
VDDQ Regulator Feedback Compensation
During S0 and S3, the external resistor (RL1) sets the current limit for the high-side switch. An internal 35 mA current sink at OCDDQ pin establishes a voltage drop
The recommended compensation network is shown in Figure 2.
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NCP5203
VTT Active Terminator in Normal Mode (S0) VTT Active Terminator Thermal Consideration
The VTT active terminator is a two-quadrant linear regulator with two internal N-channel power FETs to provide transient current sink and source capability up to 2.0 A. It is activated in normal mode in S0 when the VTTEN pin is high and VDDQ is in regulation. When in the S0 state and VTT is in regulation, signal INREGVTT will go high to notify the control logic block. The VTT regulator is powered from VDDQ with the internal FET's gate drive power derived from 5VDUAL. The VTT output voltage can be adjusted by using an external resistor divider connected to the REFSNS pin. This regulator is stable with any value of output capacitor greater than 470 mF, and is insensitive to ESR ranging from 2.0 mW to 400 mW.
VTT Active Terminator in Normal Mode (S3)
The VTT terminator is designed to handle large transient output currents. If large currents are required for very long duration, then care should be taken to ensure the maximum junction temperature is not exceed. The 5x6 QFN-18 has a thermal resistance of 35_C/W (dependent on air flow, grade of copper, and number of vias). In order to take full advantage of this thermal capability, the thermal pad underneath must be soldered directly to a PCB metal substrate.
Supply Voltages Undervoltage Monitor
VTT output is high-impedance in S3 mode.
VTT Active Terminator Fault Protection
The IC continuously monitors 5VDUAL through the 5VDUAL pin. 5VDLGD is set high if 5VDUAL is higher than its preset threshold (derived from VREF with hysteresis). The IC will later latch off if 5VDUAL is in S0 providing both VDDQEN and VTTEN remain high.
Thermal Shutdown
To provide protection for the internal FETs, bi-directional current limit is implemented, preset at 2.4 A magnitude. This current limit is also used as constant current source during VTT startup.
If the chip junction temperature exceeds 150_C, the entire IC will shutdown. The IC resumes normal operation only after 5VDUAL or VDDQEN is cycled.
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NCP5203
5VDUAL
VDDQEN
VTTEN
Soft Start
VTTEN IS DON'T CARE IN S5
VDDQ 10ms VTT in H-Z VTT thold 200 ms thold 200 ms
PGOOD
OPERATING MODE S5 S0 S3 S0 S5
5VDUAL comes out of UVLO
PGOOD goes HIGH. INREGVTT goes HIGH. INREGDDQ goes HIGH, VTT goes into normal mode.
VDDQEN goes HIGH, VDDQ is activated. VTTEN goes HIGH, VTT is not activated until VDDQ is Good.
VTTEN goes LOW to activate S3 mode and to turn off VTT, then INREGVTT goes LOW, PGOOD goes LOW.
PGOOD goes HIGH. INREGVTT goes HIGH.
VTTEN goes HIGH, VTT goes into normal mode.
Both VDDQEN and VTTEN go LOW to trigger S5 mode; VDDQ and VTT is disabled, then INREGDDQ and INREGVTT go LOW, PGOOD goes LOW.
Figure 3. Powerup and Powerdown Timing Diagram
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NCP5203
18-LEAD QFN, 5 x 6 mm MN SUFFIX CASE 505-01 ISSUE A
D
A B
PIN 1 LOCATION
E 0.15 C 0.15 C
NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINALS AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.65 0.75 0.20 REF 0.23 0.28 6.00 BSC 3.98 4.28 5.00 BSC 2.98 3.28 0.50 BSC 0.20 --- 0.50 0.60
0.10 C A2 0.08 C A1 A3
REF
A C
SEATING PLANE
DIM A A1 A2 A3 b D D2 E E2 e K L
D2
18 X
L
e
1 9
18 X
K
18 10 18 X b
E2
0.10 C A B 0.05 C
NOTE 3
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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NCP5203/D

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